This invention relates generally to computer memory access techniques and, more particularly, to access techniques in a memory composed of circulating shift registers. The invention may find application in charge storage memories where refreshing of stored charge is required such as well-known MOS shift registers, and particularly charged coupled device shift registers.
Charge coupled device shift registers are well-known in the art as shown by U.S. Pat. No. 3,758,794 issued to W. F. Kosonocky on Sept. 11, 1973. In such registers, information is stored as the presence or absence of charge packets of minority carriers in storage cells beneath the electrodes of the register. These packets of minority carriers are initially injected into a register from a source diffusion and are shifted from one electrode to the next by varying the voltage on the register electrodes. Various arrangements for varying the electrode voltage and clocking the registers are known using two, three or four phase voltages.
The application and technology of charge coupled devices have been discussed in number of papers, including W. S. Boyle and G. E. Smith, "Charge-coupled Devices--A New Approach To MIS Device Structures," IEEE Spectrum, July 1971; pages 18 through 27 Altman, "The New Concept for Memory and Imaging: Charge Coupling", Electronics, June 21, 1971; pages 50 through 59 and in various patents including U.S. Pat. Nos. 3,997,882 and 3,942,163 issued to D. K. Goyal on Dec. 14, 1976 and Mar. 2, 1976 respectively and U.S. Pat. Nos. 4,011,548 and 3,975,717 issued to G. Panigrahi on Mar. 8, 1977 and Aug. 17, 1976 respectively.
These articles and patents describe the physical configuration of CCD shift registers, and the required control and refresh circuitry necessary to operate the CCD registers. Particularly the manner of switching between high speed shift clocks for searching and low speed shift clocks for idle modes is illustrated.
The subject invention particularly pertains to a memory which includes an array of circulating shift registers each of which is accessible for input and/or output at one location only. The shift registers are stacked one on the other so that a matrix of data bits is formed. In the past, it has been typical to access such shift registers in a parallel manner in which successive columns of data bits make up a word. Each column is then successively accessible by clocking it to the parallel-arranged outputs of the plurality of circulating registers. This method of access is quite restrictive. For greater flexibility and utility in performing certain computer operations, it would be highly desirable to be able to access such a matrix in many other modes, for example, by column and diagonal, with the capability to switch between these modes.